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EIA JESD 22-B109:2014現(xiàn)行
Flip Chip Tensile Pull
出版：JEDEC Solid State Technology Association
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基本信息
標(biāo)準(zhǔn)編號(hào)： EIA JESD 22-B109:2014
發(fā)布時(shí)間：2014/7/1 0:00:00
標(biāo)準(zhǔn)類(lèi)別：Standard
出版單位：JEDEC Solid State Technology Association
標(biāo)準(zhǔn)頁(yè)數(shù)：16
標(biāo)準(zhǔn)簡(jiǎn)介
Describes test method applicable to flip chip die after the die and substrate solder joint is formed, but prior to application of underfill or other materials that increase the apparent bond strength. Used to assess the consistency and quality of the chip join process and solder joint integrity across a given flip chip die. Covers both Pb and Pb-free solder bumps.
標(biāo)準(zhǔn)備注
Supersedes EIA JESD 22 (07/2004)
本標(biāo)準(zhǔn)替代的舊標(biāo)準(zhǔn)
