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Hsul12 Lpddr2 And Lpddr3 I/O With Optional Odt
出版:Joint Electronics Device Engineering Council (JEDEC)

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基本信息
標(biāo)準(zhǔn)編號(hào): EIA JESD 8-22:2014
發(fā)布時(shí)間:2014/4/1 0:00:00
標(biāo)準(zhǔn)類(lèi)別:Standard
出版單位:Joint Electronics Device Engineering Council (JEDEC)
標(biāo)準(zhǔn)頁(yè)數(shù):38
標(biāo)準(zhǔn)簡(jiǎn)介
Describes the input, output specifications and ac test conditions for devices that are designed to operate in the High Speed Unterminated Logic (HSUL_12) logic switching range, nominally 0 V to 1.2 V.
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